Chiplet Collaboration at the Package Level: Univeristy of California, Irvine Introduces Open Package-Level Ecosystem
In the world of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) is making waves as a promising solution for high-bandwidth, low-latency interconnects between chiplets. The UCIe Consortium, which manages the open chiplet standard, recently showcased practical applications of UCIe at the TechXchange event.
UCIe 2.0, the latest standard, adds new features like the optional UCIe DFx Architecture (UDA). Notably, UDA is vendor-agnostic, ensuring compatibility across various chiplet designs. This standard is fully backwards compatible, making it a seamless upgrade for existing systems.
The TechXchange event was a platform for showcasing UCIe applications, with real-world examples provided by companies like Global Unichip Corp. (GUC) and Cadence. GUC taped out silicon-proven UCIe Face-Up IP on TSMC’s 5nm process, integrated with TSMC’s SoIC-X advanced packaging technology. This IP targets AI, HPC, and networking applications, delivering 36 Gbps bandwidth with adaptive voltage scaling for about twice the power efficiency, and achieves 1.5 TB/s per mm die edge bandwidth density.
Cadence, another company involved in the practical application of UCIe, has demonstrated UCIe architectures as part of the emerging open chiplet ecosystem. Although detailed case studies from Cadence are not fully expanded in the search results, it is noted that Cadence's involvement typically involves verification, IP integration, and design enablement tools to support UCIe chiplet architectures and ensure system-level interoperability and performance validation.
The event also featured a short introduction to UCIe by Brian Rea, the Marketing WorkGroup Chair at the UCIe Consortium. UDA, a feature of UCIe 2.0, supports a management fabric connecting chiplets to enhance testing, telemetry, and debugging.
In summary, the TechXchange event highlighted the practicality and potential of UCIe in the chiplet design process. With companies like GUC and Cadence actively developing and demonstrating UCIe solutions in cutting-edge processes and advanced packaging technologies, the future of UCIe looks promising.
Data-and-cloud-computing industries could significantly benefit from the latest developments in semiconductor technology, as the UCIe 2.0 standard, with its optional UCIe DFx Architecture (UDA), promises enhanced compatibility and performance for high-end applications such as AI, HPC, and networking. Technology companies like Cadence are employing UCIe architectures, leveraging their verification, IP integration, and design enablement tools to validate system-level interoperability and performance.