Measurement in Time-Domain by Mike Resso: VNA or TDR?
High-Speed Channel Design and Testing at 224 Gbps: Overcoming Major Challenges
In the realm of high-speed digital engineering, designing and testing channels at 224 Gbps presents significant hurdles due to severe signal degradation. Mike Resso, a signal integrity application scientist at Keysight Technologies, has been delving into these challenges and offering insights into best practices for overcoming them.
Major Challenges
At 224 Gbps, the channel experiences high insertion loss (typically around 40–45 dB), crosstalk (both near-end and far-end), inter-symbol interference, and noise that drastically degrade the signal quality. High-frequency effects necessitate precise PCB trace design with controlled impedance, minimal discontinuities, and careful management of via transitions and connector interfaces to reduce reflections and loss. Developing accurate interconnect models including PCB traces, connectors, cables, and even optical links requires detailed modeling and simulation to predict system-level performance.
Best Practices
To address these challenges, Mike Resso recommends employing advanced digital signal processing and adaptive equalization techniques at the receiver to mitigate channel impairments and compensate for frequency-dependent loss and distortions. Building comprehensive simulation environments using IBIS-AMI models and S-parameter data across the entire channel can help forecast error rates and ensure an open eye and low BER before silicon validation.
Strict PCB design rules should be implemented for trace impedance control, minimizing discontinuities, using low-loss materials, and optimizing layer stack-up and routing to preserve signal integrity. Comprehensive channel characterization is crucial, and Mike Resso suggests using Time Domain Reflectometry (TDR) for identifying and locating impedance discontinuities and faults on the channel with high spatial resolution. Utilizing a Vector Network Analyzer (VNA) with bandwidth extending beyond the Nyquist frequency (at least up to 40 GHz or more) can measure S-parameters that characterize insertion loss, return loss, and crosstalk of the channel components. Extracting accurate S-parameters for simulation input and to validate the physical channel behaviors enables margin analysis under process, voltage, and temperature variations.
Hardware validation is essential once silicon is available, as testing actual interconnects using measured BER and crosstalk values can close the loop between model predictions and real-world performance.
Tools and Techniques
Mike Resso highlights the value of using time and frequency domains for simulation and measurements on a given channel design, as it provides a versatile insight into optimizing the design for high speed. He emphasizes the flexibility of a scalable Vector Network Analyzer (VNA), like the PXI VNA, which can be configured from 2 ports to 32 ports. Mike Resso also explains that MOI stands for a method of implementation and is a recipe book for making specific measurements for any application using the Keysight Vector Network Analyzer.
In high crosstalk environments, an instrument with a high dynamic range, such as a Vector Network Analyzer (VNA), is necessary to pull a small signal out of the noise. Calibration techniques of a Vector Network Analyzer (VNA) are more sophisticated due to the high-frequency content that needs to be accurate. Mike Resso recommends the use of the Physical Layer Test System software, a tool built for digital design engineers, to identify and resolve the root causes of signal integrity problems.
Conclusion
In summary, designing channels for 224 Gbps requires a holistic signal integrity methodology combining advanced DSP, meticulous PCB design, accurate multi-domain simulations, and thorough testing using TDR, VNA, and S-parameter analysis tools to ensure reliable high-speed data transmission with acceptable BER margins. Mike Resso's recent activity has focused on this topic, and his expertise in the field offers valuable insights for engineers working in high-speed digital engineering.
[1] Resso, M. (2021). Designing Channels for 224 Gbps. Keysight Technologies. [2] Resso, M. (2021). Complete Multiport Characterization of High-Speed Digital Interconnects. Keysight Technologies. [3] Resso, M. (2021). Time Domain Reflectometry (TDR) in High-Speed Digital Engineering. Keysight Technologies. [4] Resso, M. (2021). Vector Network Analyzer (VNA) Applications in High-Speed Digital Engineering. Keysight Technologies. [5] Resso, M. (2021). The Signal Integrity eBook. Keysight Technologies.
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